# Ultra-Narrowband Filtering

In May 2018 a new patent was filed on an ultra-narrowband filtering technique. This generalizes some of the previous Prism-based filtering work by defining a generic bandpass filter design, created from 3 pairs of Prisms. For desired central frequency *c* Hz and passband bandwidth b Hz, simple formulae may be used to calculate the corresponding values of *m* and *h* for each of the six filters.

The frequency response of the filter is shown below, Here the bandwidth is defined such that the relative gain in the region [-*b*/2, + *b*/2] remains within the range -3 … 0 dB. In other words, the region of length *b* Hz, centred on *c* Hz, has a relative gain always in excess of -3dB. Given this definition of *b*, other characteristics of the filter are readily defined, as follows:

• The gain drops to -40 dB at ± 1.55 *b* Hz

• The gain drops to -80 dB at ± 2.42 *b* Hz

The design procedure works well in practice. For example, the figure below show both the theoretical design and the actual numerical performance of a Prism-based bandpass filter with the following criteria: sample rate = 40 MHz, central frequency = 1 MHz, bandwidth = 10 Hz.

There are two aspects of this design process that are particularly useful. Firstly, note the filter length is approximately 7.7 million samples. Despite this length, the filter design is effectively instantaneous, because the equivalent of the filter coefficients are simply linearly spaced sine and cosine values corresponding to the *m* and *h* values for each of the six Prisms. So, arbitrarily long filters can be designed in real time using a simple procedure. Secondly, the filtering calculation is fast, despite the filter length. This filter required 0.39 ms per sample to execute, using a single thread on an Intel Xeon E5-2630 processor, running at 2.3 GHz, and with 32 Gb RAM. The evaluation of a conventional, non-recursive, 7.7 million sample FIR filter in 0.39 ms would require a computational load (based on 2 x filter length/computer time per sample) of 39 Teraflop/s. This illustrates the computational efficiency provided by Prism signal processing. Larger filters have been simulated on the same PC: the only limitation is available memory.

In further work, this filter design procedure has been implemented in a demonstrator system consisting of a host PC and an FPGA card, which implements the Prism filters. This work has been carried out with the assistance of Entegra who loaned equipment and implemented the FPGA programming.

The figure below outlines the implementation:

In addition to the six filter Prisms, the FPGA includes a tracker Prism so that the PC host can perform frequency/amplitude/phase calculations on the filter output. The FPGA accesses the PC memory to enable large Prism filters to be stored and operated. A PC-based user interface facilitates the design and instantiation of new filters.

An example of the experimental results obtained from the system is shown below. Here, the sampling rate is 2 MHz, the central frequency is 5000 Hz, and the passband bandwidth is 0.02 Hz. This results in a bandpass filter of order 192 million, and an equivalent DSP performance of 384 TMAC/s. Note that this significantly exceeds the nominal maximum DSP performance of the Artix-7 FPGA used, which is approximately 1 TMAC/s. This higher performance arises from the recursive FIR calculation used in Prism signal processing.

The input signal, obtained using a signal generator, consists of a desired frequency component at 5000 Hz, with an amplitude of 1 mV zero-peak, combined with an interference signal at 5000.1 Hz (i.e. at a distance 5*b* from the central frequency, *c*) with an amplitude of 1 V zero-peak (i.e. 1000 times greater than the adjacent signal component to be tracked).

The figure below shows the frequency spectrum of the combined input signal around the central frequency 5000 Hz; the two adjacent frequency components with their respective amplitudes are clearly discernable.

The next graph shows the frequency spectrum of the bandpass filtered signal. The noise floor, which in the figure above is steady at around 1e-5 V, has dropped to around 1e-8 V at a distance of 0.5 Hz or greater from *c*. As intended, the interfering signal at 5000.1 Hz has been effectively attenuated, leaving the desired signal component at 5000Hz as the highest peak.

Finally, the figure below shows the amplitude of the 5000 Hz component calculated by an RST (which uses the outputs of the FPGA-based tracker Prism). The amplitude remains with 5% of its nominal value of 1 mV.

This work has been submitted in papers to a forthcoming conference, which include further examples, such as tracking dynamic change in the desired frequency component after narrowband filtering.